Chinese AI chip design is converging on a clear target: large models. On October 26, Cambricon chairman and CEO Chen Tianshi said the company's next-generation intelligent processor microarchitecture and instruction set will be optimized specifically for training and inference workloads across natural language processing models, video and image generation models, and vertical-domain LLMs.
AI Chip Competition Starts With the Ecosystem, Not the Specs
Chen listed programmability, ease of use, performance, power, and area as the improvement axes. The combination is telling: the first two address the ecosystem gap — however strong the raw compute, chips that are awkward to program and costly to migrate to will struggle to pull workloads away from Nvidia's CUDA ecosystem. Performance, power, and area are the hard metrics data-center buyers weigh in procurement.
Treating training and inference as equal priorities also matches the market's revenue structure: training workloads concentrate in a handful of leading firms, while inference workloads are growing fast as LLM applications spread — the broader incremental market for AI chips.
Domestic AI Compute: From Usable to Preferable
As one of China's leading AI chip designers, Cambricon's iteration cadence directly shapes the compute options available to domestic LLM developers. If the new microarchitecture lands on schedule, it pushes domestic AI silicon further along the path from "usable" to "preferable," riding rising demand for local compute.
Two things are worth tracking: the new processor's specifications and mass-production timeline, and — more importantly — actual adoption in customer training workloads, which is the ultimate test of ecosystem building.